Motion detector for weighing apparatus

ABSTRACT

A detector for detecting the change in the number of pulses in serially applied pulse streams by memorizing a function representing the preceding one of the two pulse stream and by comparing the memorized function with a corresponding function of the subsequentially occurring one of the two pulse streams. This detector is, among other things, applicable to sense relatively small movements of a load-receiving structure (such as a weigh hopper or platform) in a weighing system.

United States Patent Gile July 4, 1972 [54] MOTION DETECTOR FORWEIGI'IING 3,124,206 3/1964 Burke ..177/210 APPARATUS 3,318,402 5/1967Kendrick. ..177/50 3,458,001 7/1969 Pfister ..177/l64 I721 lnvemor-R'chard Rutlani VL 3,476,198 11/1969 Francis.... ..177/50 [73} Assignee:I-Iowe Richardson Scale Company, Clifton, 3,484,813 12/1969 v -.1 NJ,3,493,773 2/1970 Power ..235/I5l.33

I Filcdi M rch 12, 1971 FOREIGN PATENTS OR APPLICATIONS 1 1 pp N01123,764 743,530 1/1950 Great Britain 177/50 52 us. c1 ..177/3, 177/25,177/50, EMMWPMICF'S- Ward 177/164, 177/210, 177/1310. 3, 235/151.33Emma" [51] lnt.CI ..G0lg23/l0,G0lg23/365,GOIg 23/37 [58] Field ofSearch..177/1, 50, 25, 210, 21 1, 164, 1 1 ABSTRACT v 177/DIG' 3; 42 Adetector for detecting the change in the number of pulses in I seriallyapplied pulse streams by memorizing a function representing thepreceding one of the two pulse stream and by [56] References cuedcomparing the memorized function with a corresponding UNITED STATESPATENTS function of the subsequentially occurring one of the two pulsestreams. This detector is, among other things, applicable to 2,697,58012/1954 sense relatively small movements of a load-receiving structure3,035,648 5/1962 (such as a weigh hopper or platform) in a weighingsystem. 3,039,686 6/1962 3,063,635 1 1/1962 Gordon ..177/DIG. 8 25Claims, 4 Drawing Figures a AMPLIFIER CIRCUIT FILTER DECODER 8 DISPLAYSHEET 2 BF 2 PKTENTEDJU 4 I972 I INVENTOR RICHARD H. GILE ATTORNEYS OCD3% IOIOIOIO IOIOOICJ 1 MOTION DETECTOR FOR WEIGHING APPARATUS FIELD OFINVENTION This invention relates to systems for detecting changes indata samples and is particularly applicable to motion detectors forsensing motion of the load-receiving structure in a weighing apparatus.

BACKGROUND In recent years it has become customary to support aloadreceiving structure, such as a weighing platform or hopper, by astrain gauge load cell assembly. In platform scales, for instance, theload-receiving platform may be supported directly at each corner by aload cell, and the potentials produced by the load cells are summed upto provide a DC. signal voltage representing the weight of the loadapplied to the weighing platform.

As is well known, the application of a load to such a load cellsupported weighing platform or other load-receiving structure causes asmall, but significant deflection of platformsupporting load cellassembly, and theload cell output potential will be proportional to theforces exerted by the platform and the load on the platform. Owing tothe yieldable support provided by the load cell assembly, the load, theplatform, and the yieldable load cell support constitute an oscillatorysystem. Thus, the system, and hence the load-cell developed outputpotential, go through several oscillations when a load is applied to theplatform. Additional oscillations will be introduced if the load ismoving, owing to the kinetic energy associated with the moving load.

It, therefore, will be appreciated that inaccurate weight measurementsmay be obtained if the load cell developed potential is utilized whileit is still unstable or oscillating. Such inaccurate weight measurementmay be manifested in a read out of the weight of the applied load. Also,inaccurate weight measurements may be manifested in the delivery ofinaccurate amounts of materials to a weight hopper in a batch weighingsystem that utilizes the load cell-developed potential to control thedelivery of the materials. I

It therefore is desirable to detect the motion of the scale equipment toprovide an indication when the scale has stabilized. However, motiondetecting equipment proposed and utilized prior to this invention wasfound to be incapable of adequately sensing the relatively smallmovements of a load cell-supported, load-receiving structure. Forexample, tachometers, which have been used heretofore, areunsatisfactory for accurately sensing the small movement of a loadcellsupported scale platform.

SUMMARY AND OBJECTS OF INVENTION One major object of this invention isto provide a novel mo tion detector that is sufficiently sensitive toaccurately sense the relatively small movements of a loadcell-supported, loadreceiving structure in a weighing system.

The motion detector of this invention digitally compares representationsof successive weight-representing pulse trains that are produced by ananalog-to-digital convertenThe input of the analog-to-digital converteris connected to the load cell circuit to periodically sample the loadcell-developed potential and to convert each sampled potential into atrain of pulses in which the number of pulses in the train isproportional to the level of the load cell developed potential.

With this information, the digital comparison is accomplished by firstcounting the pulses in a given pulse train to provide a binary numberthat is representative of the number of counted pulses. Moreparticularly, the circuit of this invention retains at least the leastsignificant eight-bit binary number of a multi-bit data word that isequivalent to the number of counted pulses. The retained,count-representing binary number is electrically compared with apreviously produced and stored, count-representing binary number bysubtracting one number from the other. If the difference deviates fromzero by a predetermined magnitude, the previously'stored number isreplaced by the number with which it was compared. Butif the differenceis zero or smaller than the signal to cause a printer to print out theweight of the load on the scale. Thus, in absence of the signalcondition the printer is prevented from printing erroneous informationwhile movement of the system is taking place.

By employing successive pulse trains produced by the analog-to-digitalconverter to achieve the desired digital comparison, this inventionutilizes the high resolution of available converters. For example, onecommercially available analogto-digital converter will produce 20,000pulses for an amplified load cell potential of 7.2 volts. The digitalrepresentation therefore constitutes 20,000 divisions or equal parts ofthe 7.2 volt signal. The motion detector circuit of this invention isable to detect a difference as small as one pulse between successivelyproduced pulse trains with a relatively high degree of accuracy. Ittherefore will be appreciated that the detector of this invention ishighly sensitive and iscapable of detecting very small movements.

In the following embodiment, the motion detector of this invention isdescribed as applied to a platform scale. It will be appreciated,however, that this invention may be applied to any form of weighingapparatus where it is desired to detect the motion of the load-receivingstructure.

In addition to comparing data samples that are representative of weight,the detector of this invention is also applicable for comparing otherdata or information. For example, the detector of this invention may beutilized to detect changes in the number of pulses in two teletypemessages. If the pulse repetition frequencies of the compared pulsestreams are the 7 same, the result will be a comparison of the lengthsof the two pulse streams. This invention may also be utilized to detecta change in frequency in two pulse streams, and in such an applicationthe pulse repetition frequency may be a function of weight or otherdata.

Accordingly, another major object of this invention is to provide anovel detector for senSing changes in serially applied signals.

A more specific object of this invention is to provide a novel detectorfor detecting a change between two serially applied signals bymemorizing a representation of the preceding signal and by comparing thememorized representation with a corresponding representation of thesubsequently applied signal.

DESCRIPTION OF DRAWINGS DETAILED DESCRIPTION The embodiment shown inFIG. 1 and incorporating the principles of this invention comprises aplatform weighing system having a weighing platform 20 and an assemblyof load cells (two shown) 22 supporting platform 20. Load cells 22 areconventionally arranged one at each of the four comers of platform 20,and platform 20 is arranged to receive a vehicle,

such as a truck, or a container. Each of the load cells 20 may be of theconventional silicon or resistance strain gauge type and is excited by asuitable DC. power supply source indicated at 24.

It will be appreciated that the algebraic summation of the load celloutput signal voltages may be summed up in suitable, conventionalconditioning and amplifying circuit indicated at 28.

Since the summed output signal voltage developed by the load cellassembly in this embodiment will be proportional to the weight ofplatform 20 as well as the weight of .the load placed on platform 20, adead weight tare adjustment is provided for by a potentiometer 30 havinga moveable wiper or arm 32 which is adjustable along a resistor 34.Resistor 34 is connected across a suitable source of DC. power, asshown. The voltage impressed on wiper 32 is conventionally applied to asuitable summing junction in circuit 28 along with the load cellassembly output signal voltage. The load cell assembly output signalvoltage and the dead weight potentiometer signal voltage will beopposite in sign. Wiper 32 is adjusted to offset or tare out the weightof scale parts acting on the load cell assembly to thereby provide azero signal voltage condition at the output of circuit 28 when no loadis on platform 22. Thus, the signal voltage at the output of circuit 28will be closely proportional to the load placed on platform 20.

An additional potentiometer 36 is advantageously provided for taring outthe weight of a truck or container so as to afford a read out of theweight of a load in the truck or container. Potentiometer 36 comprises aresistor 38 connected across a suitable source of DC. power supply and amoveable wiper or arm 40 adjustable along resistor 38. The voltage onwiper 40 is advantageously applied to the summing junction that the deadweight potentiometer signal voltage is applied to in circuit 28, and thepolarity of the signal voltage developed on wiper 40 will also beopposite to that of the load cell assembly output' signal voltage. Thus,the load cell assembly output signal voltage may selectively be reducedby a magnitude corresponding to the weight of the truck or container onplatform 20 by adjusting potentiometer 36.

If it is desired to read out the gross weight (i.e., the weight of thetruck or container and the load therein), potentiometer 36 is set toprovide a zero voltage condition on wiper 40. Thus, the level of theanalog DC. signal voltage at the output of circuit 28 will beproportional to the gross weight. If it is desired to read out the'netweight (i.e., only the weight of the load delivered to the truck orcontainer on platform 20), potentiometer 36 is selectively adjusted inthe previously described manner. The level of the analog DC. signalvoltage at the output of circuit 28 will therefore be proportional tothe weight of the load in the truck or container on platform 20. Thegain of circuit 28 is conventionally adjustable.

With continued reference to FIG. 1, the DC. weightrepresenting,amplified output signal voltage of amplifier circuit 28 is applied to afilter 44 which filters out any A.C. component that may be superimposedon the DC. signal. Desirably, filter 44 is of the low pass type havinggood frequency and time response characteristics to develop a filteroutput signal which is substantially free of A.C. components that mightinterfere with the trouble free operation of the system.

The amplified and conditioned, load cell-developed signal voltage at theoutput of filter 44 is applied to the input of an analog-to-digitalconverter 50. Converter 50 is of suitable, ap propriate form forproducing a digital representation that is related to the level of theweight-representing analog signal voltage applied to the input of theconverter. In this embodiment, the digital representation is in the formof a fixed frequency pulse stream or train having equal time separationsbetween pulses. The number of pulses in the stream is proportional tothe level of the weight-representing analog signal voltage at a timewhen the analog signal is sampled.

Converter 50 advantageously is of the conventional dual ramp type. Inthis type of analog-to-digital converter, the analog signal voltageapplied to the input of the converter is integrated over a fixed,predetermined time period in response to a triggering signal from asample rate trigger circuit 52. The resulting ramp voltage that isgenerated is initiated from a predetermined voltage level such as zerovolts. The slope of the ramp will be proportional to the level of theanalog signal voltage at themoment it was sampled. During the generationof this fixed time base ramp voltage, a train of fixed frequency pulsesfrom a clock in the analog-to-digital converter are serially routedthrough a gate to a multidecade BCD (Binary Coded Decimal) countercircuit generally indicated at 54 in FIG. 1.

In this embodiment, the range of converter 50 is, by way of example,zero to 20,000 pulses, and the pulse count loaded into counter circuit54 during the fixed time base integration is 10,000 pulses. This pulsecount (10,000 pulses) fixes the time interval of the first integration,and when the last of 10,000 pulses is loaded-into counter circuit 54,counter circuit 54 supplies a reset signal over a line 56 to converter50.

This reset signal switches converter 50 from the output of filter 44 toa suitable source of reference voltage as indicated at 58 in FIG. 1.Converter 50 will now integrate the analog reference signal. This resetsignal is also operative through a logic circuit 57 to reset countercircuit 54 to zero.

The'polarity of the reference signal from source 58 is so related to theanalog signal supplied by filter 44 that integration of the referencesignal is in the opposite direction as compared with the direction inwhich the filter output signal was integrated. Thus, a second ramp isgenerated starting from a voltage at which the first ramp wasterminated, and this second ramp will be started in response to thereset signal from counter circuit 54. The slope of this second ramp isconstant and proportional to the fixed reference voltage level, and

' during the time interval that the reference signal is beingintegrated, the converter clock pulses are routed by line 60 to countercircuit 54.

When the second ramp reaches the voltage level from which the first rampwas initiated, converter 50 supplies a latching signal over line 62 to alatching network 64. Latching network 64, as will be described ingreater detail later on, is connected to the output of counter circuit54, and when the latching signal is received from converter 50 itlatches in and thereby memorizes the BCD output of counter circuit 54.It will be appreciated that the time interval of the second ramp andthus the number of converter pulses loaded into counter circuit 54during this second time interval will be substantially proportional tothe level of the analog signal supplied by filter 44 at the time that iswas sampled.

Trigger circuit 52 may be of any suitable appropriate form, and it maybe incorporated as part of converter 50. One form of trigger circuitprovides a saw-tooth like signal voltage by cyclically charging anddischarging a capacitor. The repetition rate of the saw-tooth signalvoltage will determine the rate at which the weight-representing analogsignal voltage is sampled.

Counter circuit 64 may be of any appropriate conventional form and isshown to comprise a series of conventional BCD electronic decadecounters 70, 71, 72, 73 and 74 each having a four-bit, l-2-4-8 BCDoutput and respectively representing the units, tens, hundreds,thousands and tens of thousands digits in a weight-indicating,multi-digit decimal number to be displayed by a visual, digitaltranslator and display device 76. Counter 70-74 advantageously are themonolithic type Ser. No. 7490 having a divide-by-two stage and adivide-by-five stage.

The truth table or BCD count sequence for each of the counters 70-74 isshown in FIG. 2. Each counter will automatically reset when the signallevel at its D pin changes from a high (a logical 1) to a low (a logical0) at the tenth pulse. With the illustrated connections, each of thecounters 70-73 will supply the count of l to the next succeeding counterfor every 10 counts coming into the counter. It will be appreciated thatthe number of counters employed in circuit 54 will depend upon thenumber of decades that are desired in the number to be displayed.

Still referring to FIG. 1, latchnetwork 64 comprises a series 4 of BCDdata word storage or memory latches 80, 8.1, 82, 83 and 84, one for eachof the counters 70-74. Latches 80-84 advantageously are of the four-bitquad type Ser. No. 7475, each having four storage devices for storing afour-bit data word and the complement thereof. For this purpose each ofthe four storage devices in each latch has a Q and 6 output asindicated. Each storage device also has a data bit input pin and amemory or latch pin. The data words to be stored in latches 80-84 aresupplied by counters 70-74 respectively.

For the foregoing type of latch, the latching signal line 62 isconnected to the latch pin of each storage device in latches 80-84. Whenconverter 50 supplies the proper logical state on line 62, whateverbinary states that are present on the data input pins of latches 80-84will be stored on the Q output pins of the latches, and the complementswill be stored on the 6 output pins.

As shown, the outputs of counters 70-74 are connected in parallel tolatches 80-84. The information in counters 70-74 is thereforetransferred in parallel to latches 80-84 respectively, Latches 80-84memorize this information when the proper latching logical state issupplied by converter 50 as previously described.

The Q output pins of each of the latches 80-84 are connected in parallelto one module in device 76. In this embodiment device 76 will have fivemodules, one for each of the latches 8084. Device 76 may be of anysuitable, conventional form for accepting a BCD input at a relativelylow voltage level and for generating at each module the correspondingdecimal output 0 through 9. One type of device 76 is Sigma 7, Model 32,manufactured by Sigma Instruments, Inc. of Boston, Mass. In convertingback to decimal form, the truth table in FIG. 2 may be utilized todetermine the number that device 76 will display in response to the datainformation latched on the output pins of latches 80-84.

The BCD data information latched in or memorized by latches 80-84 isalso applied to a printer solenoid and solenoid driver circuit 90 ofappropriate, conventional form. Energization of printer solenoids incircuit 90 actuates type in a conventional printer 92 in a known manner.Through suitable logic in circuit 90, the BCD data information appliedto circuit 90 selects the printer solenoids to be energized when poweris applied through a switch circuit 96 from a suitable power supplysource 94.

Switch circuit 96 may comprise a suitable solid state switch orswitching arrangement which is responsive to a switch control signal tocomplete the circuit connection for applying the power supply voltage tocircuit 90 for energizing those printer solenoids that are selected bythe applied BCD data information from latches 80-84. Switch circuit 96is responsive to the removal of the switch control signal to disconnectthe power supply from circuit 90.

From the foregoing it is clear that when a load is placed on platform20, the load cell assembly will produce a DC. analog signal voltage thatis conditioned and amplified by circuit 28. The level of the DC. analogsignal voltage at the output of circuit 28 will be proportional to theGross weight or net weight of the load depending upon the selectedsetting of potentiometer 36 as previously described. Thisweight-representing analog signal voltage is applied through filter 44to the input of converter 50,

In response to each successive trigger signal supplied by circuit 52,converter 50 samples the analog signal voltage at its input by firstintegrating the sampled analog signal and then integrating the referencesignal from source 58. During integration of the weight-representinganalog signal voltage from filter 44, the pulses produced by converter50 are counted by counter circuit 54, and when the pulse count reaches10,000, a logical 1 will be provided on the A pin of counter 74. Thislogical state will be inverted and transferred by line 56 to cause theintegrator in converter 50 to switch from filter 44 to source 58 at theproper time. It will be ap preciated that counters 70-74, in countingthe number of pulses in each pulse train that is supplied by converter50,

produces the equivalent 8-4-2-1 BCD data information at their outputpins.

As shown in FIG. 1, the signal on line 56 is inverted again and appliedto an And gate 102 in circuit 57. The other input of gate 102 isconnected to the complementing output pin6 of a dual D flip flop 104which, in this embodiment, is the type Ser. No. 7474. The signalcondition on line 56 is applied without further inversion to the pre-setinput pin of flip flop 104, as shown. After each conversion and inresponse to the next trigger signal, converter supplies the counterreset signal to line 98. The reset signal on line 98 is applied to an ORgate 108. In addition it is inverted and applied to the clear pin offlip flop 104 as shown. The output of And gate 102 is connected to theother input of OR gate 108, and the output of OR gate 108 is connectedby a line 110 to the reset pins of counters 70-74.

After each analog-to-digital conversion and in response to the nexttrigger signal supplied by circuit 52 converter 50 supplies a logical lto line 98, and this signal condition is ored through gate 108 to resetcounters 70-74 to zero in preparation for the next conversion. Inaddition, a logical 0 will be applied to the clear pin of flip flop 104.This signal condition together with a logical 0 at the pre-set pin offlip flop 104 will change the state at the 6 output pin of the flip flopto a logical 1. At this point, however, no information will be Anded 7through gate 102 since the logical state on line 56 is inverted beforeit is applied to gate 102. At this time, therefore, the signalconditions at the input to gate 102 will be a 0 and a I.

As previously mentioned, converter 50, in response to the trigger signalfrom circuit 52 integrates the filter output voltage, and during thistime, the converters clock pulses are gated through to counter circuit54. In this embodiment counter circuit 54 will be counting every pulse,and when the 10,000th pulse is counted in, a logical l is applied to theA pin of counter 74 and inverted, and the inversion is applied to line56. Now the signal condition at the input to gate 102 will change tosupply a logical 1 through gate 108 to reset the counters to zero. Inaddition the logical state supplied by line 56 will cause converter 50to switch over to the reference source 58, and converter 50 contains thelogic to block further spurious switch over signal conditions until thenext conversion. Also a logical l and a logical 0 will respectively beapplied to the clear and pre-set pins of flip flop 104, causing thestate on the 6pin to change to a logical 0. This condition will preventresetting of the counters in the event that the number ofconverter-produced pulses supplied during generation of the second rampequals or exceeds 10,000. That is, a logical 1 at the A pin of counter164 will not reset the counters in the count-in of theweight-representing pulse train.

As the reference signal from source 58 is integrated, converter 50 willsupply the weight-representing pulse train to counter circuit 54, andthe number of pulses in this train will be proportional to the level ofthe sampled analog signal supplied by filter 44. At the completion ofthe integration of the reference signal from source 58 (i.e., when thesecond ramp reaches the level from which the first ramp was initiated),the supply of further pulses from converter 50 is blocked, and countercircuit 54 will now have counted in the number of pulses in thisweight-representing pulse train. At this time, converter 50 isresponsive to supply a latch signal over line 62 to latches -84. Inresponse to this latch signal latches 80-84 transfer the BCD data wordssupplied by counters 70-74 to their output pins Q, and to latch in ormemorize the transferred BCD data words at their Q output pins. Thetransferred BCD data information will be latched in uncomplemented format the Q output pins, and the complements of the transferred BCD datawords will be latched in on the 6 pins of the latches. Upon latching inthis new information, the old information on the Q and 6 pins of latches70-74 is removed.

The memorized, weight-representing BCD data information at the Q outputpins of latches 80-84 is applied to device 70 which decodes theinformation to display the weight in decimal form. In addition, theweight-representing BCD data information latched in at the Goutput pinsof latches 80-84, is applied to circuit 90 to select those printersolenoids that will be energized when switch circuit 96 is actuated toapply the power supply voltage from source 94 to circuit 90. It will beappreciated that the printer solenoids will be energized only whenswitch circuit 96 is actuated to complete the electrical circuitconnection between source 94 and circuit 90, and switch circuit 96 willbe actuated only when the previously mentioned switch control signal isapplied to circuit 96 over a line indicated at 99 in FIG. 1. I

In response to the next trigger signal suppliedby circuit 52, converter50 again samples the weight-representing analog signal voltage at itsinput. Converter 50 also responds by supplying a reset pulse over line98, and this reset pulse is ored through gate 108 toreset counters 70-74to zero in preparation for counting the next pulse train.

The circuitry thus far described and including counter circuit 54 andlatch network 74 may be the same as that described in the US. copendingapplication Ser. No. 58,260 filed on July 27, 1970, assigned to theassignee of the instant application and entitled System.

The switch control signal is applied to line 99 bythe digital motiondetector circuit of this invention. The motion detector circuit isgenerally indicated at 120 in FIG. 1 and is effective to prevent aprint-out of the weight-representing data information by printer 92until the motion of platform reduces to a predetermined magnitude andpreferably to an essentially static or stable condition.

As is well known, the application of a load to the platform causes asmall, but significant deflection of the platform supporting load cells,and the load cells produce an electrical output potential proportionalto the deflection induced by the forces exerted by the platform and theload on the platform. Owing to the yieldable support provided by theload cells, the load, the platform and the yieldable load cell'supportconstitutes an oscillatory system. Thus, the deflection measured by theload cells, and hence the load cell-developed output potential, goesthrough several cycles of oscillation when a load is applied to theweighing platform. Additional oscillations will be introduced if theload is moving due to the kinetic energy associated with the movingload.

It therefore will be appreciated thatinaccurate weight measurements maybe obtained if the read out is made while the oscillations areoccurring. This objectionable condition is particularly prevalent inhighly sensitive, high speed weighing systems such as the one thus fardescribed.

According to this invention motion detector circuit 120 provides anindication of when the scale attains a stabilized condition after a loadis applied to platform 20. That is, circuit 120 will effectively detectthe motion of platform 20 and will provide an indication when theplatform has stopped moving.

By utilizing this detection to control operation of printer 92, printingof the weight will automatically be prevented until the oscillationscease.

As shown in FIG. 3, circuit 120 comprises a pre-stage divider 130, twocyclic four-bit binary counters 132 and 133, four four-stage flip flopquad latches or memory circuits 136, 137, 138 and 139, two four-bitbinary adders 142 and 143, a logic circuit indicated at 146, and anacceptable-condition binary counter 148.

The purpose of divider 130, as will be described in detail later on, isto divide the number of pulses in the pulse train produced by converter50 by a pre-selected divisor, so that the quotient of the division willbe applied to and counted by counters 132 and 133. For this purpose,divider 130 may be of any appropriate, conventional form and isadvantageously of the Ser. No. 7490N type having a divide-by-two stageand a divide-by-five stage.

EAch of the counters 132 and 133 is of suitable conventional form forcounting-the number of pulses or counts in a train and for supplying theequivalent four-bit binary number for the number of counts that arestored. For this purpose counters 132 and 133 are advantageously of theSer. No. 7493N type.

As shown, the pulses to be counted are supplied from an input pin 149 tothe input of counter 132. Counter 132 will count each incoming pulse,and after each sequence of 16 pulses it will reset to zero and supply acarry count over a line 150 to the input of counter 133. After eachsequence of 16 transferred pulses counter 133 also resets to zero. Itwill therefore be appreciated that counters 132 and 133 areinterconnected to provide an eight-bit binary counter for storing up to256 counts. Thus after each sequence of 256 incoming pulses counters 132and 133 return to their original states. In effect, therefore,theeight-bit binary counter circuit provides for the division of theincoming count by 256 and stores the remainder. This enables the lessersignificant remainders to be utilized in a digital comparison by adders142 and 143.

Each of the quad latches 136-139 is of suitable, conventional form formemorizing a four bit binary number in response to a latching signal.Each quad latch is advantageously of the Ser. No. 7475N type having fourdata input pins, one for each of its D type flip flop stages. Each ofthe flip flop stages also has a latch pin, a Q output pin and a 6 outputpin. As previously described, each of the latches 136-139 is responsiveto the application of a latching signal to its latching pins to transfera four-bit binary data word at its data input pins to its Q output pinsand to latch or memorize the transferred data word at its Q output pins.At the same time, the complement of the transferred and latched dataword will be latched in on the 6 output pins of the latches.

As shown in FIG. '3, the binary data word output pins of counter 132 areconnected in parallel to the data input pins of latch 136, and thebinary data output pins of counter 133 are connected in parallel to thedata input pins of latch 137. The pulse trains successively produced byconverter 50 are applied directly to pin 149 or through divider to pin149 as will be explained in greater detail later on. The latch signalline 62, in addition to being connected to latches 80-84 is alsoconnected to a latch input pin 152 at detector 120. Pin is connected bya line 152 to the latch pin of each flip flop stage in latches 136 and137.

Thus, the latch signal supplied by converter 50 to latches 80-84 is alsosupplied to latches 136 and 137. Therefore, at the same time latches80-84 memorize the information supplied by counters 70-74, latches 136and 137 will memorize the binary information supplied by counters 132and 133 respectively.

EAch of the adders 142 and 143 is of appropriate, conventional form foradding two four-bit binary numbers. These adders are advantageously ofthe Ser. No. 7483N type having two sets of four-bit data input pins asshown.

The Q output pins of latch 136 are connected in parallel to the fourdata input pins of latch 138. Also, the 0 output pins of latch 136 areconnected in parallel to the four data input pins of one set at adder142. The 6 data output pins of latch 138 are connected in parallel tothe other set of input pins at adder 142 as shown. The four Q outputpins of latch 137 are connected in parallel to the data input pins oflatch 139, and they are also connected in parallel to the four datainput pins of one set at adder 143. The 6 data output pins of latch 139are connected in parallel to the data input pins of the other set atadder 143. Adders 142 and 143 are interconnected to provide aneight-digit adder for adding two eight-bit binary data words. Theinterconnection provides a carry from adder 142 to adder 143.

Still referring to FIG. 3, logic circuit 146 comprises a series of eightinverters 161, 162, 163, 164, 165, 166, 167, and 168 1 and twoeight-input NAND gates 170 and 172. The outputs of inverters 161-168 areconnected in parallel to gate 170 as shown. The four data output pins ofadder 143 are indicated at A, B, C and D and are respectively connectedin parallel to four inputs of gate 172 and to the input sides ofinverters -168. The four data output pins of adder 142 are alsoindicated at A, B. C and D, and they are connected in parallel to theinput sides of inverters 161-164. The data output pins B, C and D ofadders 142 are connected to three of the four remaining inputs of gate172, and the last input of gate 172 is tied to the B pin of adder 142,as shown. On each of the adders 142 and 143, the least significantbinary digit (bit) of the fourbit number is applied to the A output pin,the next to the B pin, the next to highest to the C pin, and the mostsignificant digit to the D pin.

The outputs of gates 170 and 172 are connected to a twoinput NAND gate176. The output of gate 176 is connected through an inverter 178 to oneinput of a further plural-input NAND gate 180. The other operative inputof gate 180 is connected to receive a delayed, shaped, latching signal.

As will be described shortly, the signal condition at the output of gate176 controls the application of a latch signal to latches 138 and 139.The condition at the output of gate 176 will also determine whether acount is applied to counter 148.

As shown in FIG. 3, line 152 is connected to supply the latching pulseproduced by converter 50 to a delay one-shot 184. The delay one-shot isresponsive to the latch pulse to produce a delayed latching pulse signalcondition which is shaped by a pulse shaping network 186 of suitableform and applied to the input side of inverter 190. The output ofinverter 190 is connected to one of the inputs of gate 180, as shown. I

Considering operation of the motion detector circuit thus far described,it will be assumed for this first example, that the output of converter50 is connected directly by a line 192 (FIG. 1) to pin 149 so thatdivider 130 will be out of the active circuit. When the triggeringsignal is supplied by trigger circuit 52 to converter 50, theweight-representing analog signal voltage is sampled and converter 50initially produces a train of 10,000 pulses and a counter reset pulse aspreviously described. The converter-produced reset pulse, which is gatedthrough gate 108 is applied by a line 194 (FIG. 1) to an input pin 196(FIG. 3) at motion detector 120. Pin 196 is connected to the reset pinsof counters 132 and 133 and divider 130. Thus, the converter-producedreset pulse resets counters-132 and 133 and divider 130 to zero inaddition to clearing counters 70-74.

The first train containing 10,000 pulses is applied to pin 149, andthese pulses are counted by counters 132 and 133 in the mannerpreviously described. Counters 132 and 133 will store the remainder ofthe quotient of 10,000 divided by 256. The binary data wordsrepresenting this remainder are applied to the data input pins oflatches 136 and 137, but no transfer and memorization will take placesince the latching signal is not present on line 152.

At the end of the first integration and generation of the 10,000 pulses,counter 74 supplies a reset signal through logic circuit 57 aspreviously described, and this reset signal in addition to clearingcounters 70-74 is applied through line 194 to pin 196 for resettingcounters 132 and 133 and divider 130 to zero. During the integration ofthe reference signal from source 58, the pulses in theweight-representing pulse train are gated from converter 50, applied topin 149, and counted by counters 132 and 133.

Once again, counters 132 and- 133 will store only the remainderresulting from the division of the pulse train count by 256. The binarydata word representing this remainder will be produced at the output ofcounters 132 and 133 and applied to the data input pins of latches 136and 137.

At the end of the second integration, converter supplies the previouslymentioned latching pulse which is applied through pin 150 to latches 136and 137. Latches 136 and 137 will now transfer the binary data numbersat their inputs and will latch the transferred binary information ontheir Q output pins as previously explained. By latching in ormemorizing this new information, old binary information at the outputsof latches 136 and 137 is removed.

The new binary data word latched in at the output of latch 136 will beapplied to the inputs of latch 138 and adder 142. Also, the binary wordlatched in at the output of latch 137 will be applied to the inputs oflatch 139 and adder 143. At this stage no latching signal is applied tolatches 138 and 139 so that the applied data words will not betransferred into the latches.

Binary addition of the binary numbers at the 6 output pins in latch 138and at the Q output pins of latch 136 is performed by adder 142.Similarly, binary addition of the binary numbers at the 6 output pins oflatch 139 and the 0 output pins of latch 137 is performed by adder 143.By using the binary numbers at the 6 output pins of latches 138 and 139the effect is a subtraction of the uncomplemented form of theinformation memorized in latches 138 and 139 from the new infonnationsupplied by latches 136 and 137. This will be explained in greaterdetail shortly.

As will become apparent shortly, logic circuit 146 will supply anacceptable signal condition (indicating no or negligible motion) whenthe difference between the old eightbit binary number stored by latches138 and 139 and the subsequent eight-bit binary number stored andpresented by latches 136 and 137 is not greater than the decimalnumber 1. More particularly, circuit 146 will furnish an acceptable,nomotion signal condition when a eight-bit summation at the combinedoutputs of adders 142 and 143 is any one of the following binarynumbers:

2.1lllllll 3.1llllll0 At the first addition occurring aftera load isplaced on platform 20, the binary data words memorized by latches 138and 139 will be old, uninforrnative data. They may be randon values orvalues latched in during a prior weighing cycle. Assume now that theremainder of the pulse train count that was counted and stored bycounters 132 and 133 is equivalent to the decimal number 7 and thatbinary data word memorized at this time in latches 138 and 139 isequivalent to the decimal number 5. With the previously describedcircuit connections for latches 136-l39 and adders 142 and 143. acomplement subtraction is performed to yield the difference in terms ofa binary number. That is, the addition of the complement of one binaryand the uncomplemented form of another binary number yields the binarydifference between the two binary numbers. Thus by applying to adders142 and 143 the complement of the binary number stored in latches 138and 139 and the uncomplemented binary number stored in latches 136 and137 the output of the adders will yield the difference between thestored binaryv numbers. Considering the foregoing example, thecomplement of 00000101 (the decimal number 5) will be 111111010. Thiscomplement will be added by adders 142 and 143 to the binary number00001 11 (the decimal number 7) as follows:

l l l l l 0 l 0 I carry 0000000l In the circuit of this invention thecarry is dropped in the binary substraction. Thus, the output at adder142 will be 0001, and the output at adder 143 will be 0000. With thisadder output, the binary number applied to gate 172 will be 00000000. Asa result, the output of gate 172 will be a logical 1. Also the binarynumber 00000001 is inverted by inverters 161-168 and applied to theinput of gate 170. Thus, the output of gate will be a logical 1.Consequently, the output of gate 176 will be a logical 0. This state isinverted so that at one input a logical 1 will be applied to gate 180.Before a delayed reset pulse is supplied to gate 180, the state at theother input to gate 180 will be a logical 0. Consequently, the output ofgate 180 will be a logical 1.

As shown, the output of gate 180 is connected to an inverter 196, andinverter 196 is connected by a line 197 to the latch pins at each stagein both of the latches 138 and 139. The output of inverter 196 is alsoconnected by a line 198 to the reset pin of counter 148. Thus when alogical l is provided at the output of gate 180, a logical 0 will besupplied to the latch pins of latches 138 and 139 and to the reset pinof counter 148. Therefore, no reset or latching operations will beperformed, until a delayed latch pulse is received.

The delay one-shot provides the necessary delay to allow adders 142 and143 to perform their adding operation and to present the resultinglogical states to gate 180 at the same time or before the reset pulse isapplied to the other input of gate 180. Thus, when the delayed resetpulse is applied to gate 180, all of the input condition will be high.As a result, the output of gate 180 will go low (a logical and theoutput of inverter 196 will go high (a logical 1). The output ofinverter 196 will remain high for the duration of the reset pulsesupplied to the input of gate 180. As a consequence, a positive goinglatching pulse is supplied by line 197 to latches 138 and 139, and thesame pulse is supplied by line 198 to reset counter 148 to zero.

By applying a latching pulse to latches 138 and 139, the binary numberssupplied to the inputs of latches 138 and 139 by latches 136 and 137will be transferred to and latched in at the output pins of latches 138and 139. The original binary information at the outputs of latches 138and 139 will now be replaced by the binary information supplied bylatches 136 and 137. Considering the previous example, the complement ofthe original binary word 00000101 (decimal 5) will now be replaced bythe complement of the binary word 00000111. Thus the binary number 1 l 111000 will be memorized or latched in at the Coutput pins of latches 138and 139.

As previously mentioned, counter 148 counts only the number ofacceptable comparisons made by adders 142 and 143. Advantageously,counter 148 is of the four-bit binary Ser. No. 7493N type. To controlthe supply of counts to counter 148, a three-input NAND gate 200 has oneinput connected to the output of inverter 190, a second input connectedto the output of gate 176, and a third input connected to the output ofan inverter 202. The input of inverter 202 is connected to a pin 204,and the four flip flop stages of counter 148 are respectively connectedto output pins 211, 212, 213 and 214. The logical states for the first,second, third and most significant digits in the four-bit binary numberare respectively applied to pins 211-214. A jumper 216 connects aselected one of pins 211-214 to pin 204. Pin 204 is also connected toline 99 as shown.

By selectively connecting jumper 216 to pin 211 one acceptable conditioncounted in by counter 148 will supply the switch actuating controlsignal (logical 1) through pin 204 to switch 96. It will be recalledthat switch 96 is actuated by the control signal to apply power fromsource 94 for energizing those printer solenoids that are selected forenergization by the BCD data information supplied from latches 80-84. Ifjumper 216 is connected to pin 212, then two successive acceptableconditions must be counted by counter 148 to supply the switch actuatingcontrol signal to switches 96. 1f jumper 216 is connected to pin 213,then the count-in of four successive acceptable conditions are requiredto actuate switch 96, and so on. In this embodiment, jumper 216 isconnected to pin 212, thus requiring counter 148 to count in twosuccessive acceptable comparisons of successive weight-representingpulse trains.

Considering the previous example in which the equivalent of the decimalnumber 5 was stored by latches 138 and 139 and in which the binaryremainder equivalent to the decimal number 7 was applied to the inputsoflatches 138 and 139 and to adders 142 and 143, it will be recalledthat by virtue of the digital comparison performed by adders 142 and143, a pulse signal was applied to line 198 in addition to applying thepulse signal to line 198 for latching in the new remainder present atthe data input pins of latches 138 and 139. As a result, counter 148will be reset to zero to drop out any previously stored count.

If, for example, one count indicating an acceptable condition waspreviously stored in counter 148, it will be dropped out. Thus, for theconnection shown for jumper 216 in FIG. 3, two successive acceptableconditions must be counted by counter 148 in order to change the voltagelevel at pin 212 to a logical 1.

Gate 200 and the connections thereto will block the transfer of acounter-actuating pulse to the input of counter 148 whenever a counterreset pulse is supplied to line 198. When a logical 0 is provided atoutput of gate 176 to indicate an unacceptable (i.e., unstable)condition, the state at the output of gate 200 will be a logical 1 priorto the supply of the delayed reset pulse from inverter 190. Until thecount reaches 2 in counter 148, the state at pin 212 will be a logical0, and this state is inverted by inverter 202 to apply a logical 1 togate 200. When the delayed reset pulse is supplied from inverter 190,the logical state at the output of gate 200 will not change, owing tothe presence of the logical 0 supplied from the output of gate 176. Theoutput of gate 200 is inverted by an inverter 220, and the invertedoutput is applied to the input of counter 148. Thus, for the detectionof an unstable condition, a logical 1 will be provided at the output ofgate 200 and hence a logical 0 will be applied to he input of counter148.

With the logic circuit shown in FIG. 3 it can be shown that a logical 0will be provided at the output of gate 176 whenever the differencebetween the two binary numbers compared by adders 142 and 143 is greaterthan the equivalent of a decimal number 1. Each time a logical 0 isprovided at the output of gate 176, counter 148 will be reset, thecircuit will block the transfer of a counting pulse (a logical 1) tocounter 148, and a latching pulse will be supplied to latches 138 and139, thus causing latches 138 and 139 to drop the previously memorizedinformation and to memorize the new binary information supplied bylatches 136 and 137.

In response to the next trigger signal from circuit 52, converter 50will respond by generating the first 10,000 count pulse train followedby the weight-representing pulse train, and at the beginning of theconversion, converter 50 will also supply a counter reset pulse all aspreviously described. The reset pulse, in addition to resetting counter70-74, will also reset counter 132 and 133 and divider to zero. Thefirst train of 10,000 pulses will be counted by counters 132 and 133,but this binary information will not be memorized owing to the absenceof a latching pulse on line 152 at this time. Again, the remainder ofthe division of 10,000 counts by 256 will be stored by counters 132 and133.

Upon counting in the 10,000 pulses in the first train, counter 74supplies the previously described reset signal through logic circuit 57to reset counters 132 and 133 and divider 130 to zero in addition toresetting counters 70-74 to zero. The pulses in the following,weight-representing pulse train will now be counted by counters 132 and133 in the manner previously explained.

Assume that the number of pulses in this next weightrepresenting pulsetrain is the same as that in the preceeding weight representing pulsetrain, thus indicating a stable condition for two successive samplingperiods. Considering the foregoing example, the remainder stored bycounter 132 and 133 will therefore be the binary equivalent of thedecimal number 7, namely 00000111. This binary number will be memorizedby latches 136 and 137 when converter 50 supplies the previouslymentioned latching pulse to line 150. This binary information willtherefore be latched in at the Q output pins of latches 136 and 137 inplace of the preceeding, latched information and will be supplied to theinputs of latches 138 and 139 and adders 142 and 143.

Adders 142 and 143 will now digitally compare this new binaryinformation with the complement of the binary number memorized bylatches 138 and 139.

At this stage the binary number latched in at latches 138 and 139 willbe 00000111, and the complement of this number is 11111000. Thiscomplement and the new binary number 000001 1 1 will be added by adders142 and 143 as follows:

Thus, the binary number 11111111 will be supplied at the combinedoutputs of adders 142 and 143. As a result, the inputs to gate 176 willbe a logical 1 (from gate 170) and a logical (from gate 172). Thissignal condition will provide a logical l at the output of gate 176.This signal state is applied to gate 200, and it is inverted and appliedto gate 180. When the delayed latching pulse is supplied from inverter190, the input signal conditions at gate 200 will all be high (logicalls). Thus, the state at the output of gate 200 will change from alogical 1 to a logical 0. This condition is inverted by inverter 220with the result that a positive going pulse condition (a logical l willbe applied to the input of counter 148 for the duration of the delayedlatching pulse. One count will therefore be counted in by counter 148 toplace a logical l on pin 211.

At the same time, the application of the delayed latching pulse (alogical l) to the input of gate 180 will not change the signal state atthe output of gate 180 owing to the presence of a logical 0 at theoutput of inverter 178. Thus, the signal state at the output of inverter196 will remain a logical 0. As a result, counter 148 will not reset tozero and latches 138 and 139 will not memorize the new binaryinformation supplied by latches 136 and 137.

As will become more apparent shortly, whenever a logical l is providedat the output of gate 176, a count will be counted by counter 148, andlatches 138 and 139 will not memorize the new information applied bylatches 136 and 137. Thus, latches 138 and 139 will retain the originalbinary number. It also will be appreciated that anyone of the previouslymentioned acceptable conditions at the output of adders 142 and 143(namely 00000000,llllll1l, or 11111110) will provide a logical l at theoutput of gate 176.

Assume now that the next weight-representing pulse train produced byconverter 50 has one less pulse as compared with the preceeding weightrepresenting pulse train. As a result, the remainder equivalent to thedecimal number 6 will be stored by counters 132 and 133 and memorized bylatches 136 and 137. Thus latches 136 and 137 will supply the binarynumber 000001 10 for comparison with the complement of the number storedby latches 138 and 139. It will be recalled that the number stored bylatches 138 and 139 at this stage is 00000111, the complement of whichis 11111000. Adders 142 and 143 will add this complement and the newlyapplied number 000001 10 as follows:

lllllll0 Since the output representing the least significant digit atadder 142 is not applied to gate 172, the input' to gate 172 will be 1 ll l l l l l. The outputs of gates 170 and 172 will respectively be alogical l and a logical 0. The output of gate 176 will therefore be alogical 1.

As a result, the count in counter 148 will be advanced by one and nolatching pulse will be supplied to latches 138 and 139 when the delayedlatching pulse condition is supplied to the inputs of gates 200 and 180.Now counter 148 will contain the count of two to thus change the stateon pin 212 to a logical l. This signal condition is applied by line 99to actuate switch 96. Switch 96 will therefore apply power from source94 to circuit 90 for energizing those printer solenoids that wereselected for energization by the BCD data information supplied fromlatches 80-84. In addition, the logical l at pin 212, upon beinginverted by inverter 202, will block the transfer of additionalcounter-actuating signal condition through gate 200.

If the last weight-representing pulse train produced by converter 50 hadone more pulse than the preceeding weightrepresenting pulse train, thenthe remainder equivalent to the decimal number 8 would have been storedby counters 132 and 133 and memorized by latches 136 and 137. As aresult, the binary number 00001000 would have been presented foraddition along with the binary number lllll000 at adders 142 and 143,and adders 142 and 143 would add as follows:

Under these conditions, it is evident that gates 172 and 170 willrespectively supply a logical l and a logical 0 to gate 176. Gate 176will consequently provide a logical 1, indicating a stable or acceptablesignal condition for count-in by counter 148.

It will be appreciated that the motion detector circuit provides ahighly accurate, yet relatively simplified and inexpensive means fordetecting variations in the load cell developed potential and,consequently, for detecting the movement of the load-receiving platform.By utilizing a pair of counters (counters 132 and 133) to count up to256 and corresponding pairs of latches and adders, the motion detectorcircuit shown in FIG. 3 will be accurate to one part in 256. Thisaccuracy can readily be increased by adding one or more counters tocounter 132 and 133 to provide storage space for a number of greaterthan 256. In such a case it is evident that a corresponding number oflatches and adders will also be added to the circuit. it is also evidentthat the chance of error is reduced by increasing the required number ofacceptable counts in counter It also will be appreciated that thecircuit shown in FIG. 3 is operative with one of the counters 132 and133, one of the latches 136 and 137, one of the latches 138 and 139 andon of the adders 142 and 143. In such a case the possible error would beone in 16.

In addition to the foregoing, it is clear that adders 142 and 143, inadding the two binary numbers applied to their input pins, digitallycompare the two numbers to provide the binary summation of the twonumbers.

As previously mentioned, divider 130 is utilized where it is desired toselectively divide the converter-produced pulse train before it isapplied to pin 149. As shown pins 230 and 231 are respectively connectedto the divide-by-two input stage and to the divide-by-five input stageof divider 130. The A, B, C and D outputs (respectively representing the1, 2, 4 and 8 weights in the BCD output) of divider 130 are applied topins 232, 233, 234, 235.

If it is desired to divide the number of pulses in theconverter-produced pulse train by two, then line 192 is connected to pin230 and a jumper 236 is connected between pin 232 and pin 149, as shownin FIG. 3A. Thus, the number of pulses applied to pin 149 will beone-half the number supplied in the converter produced pulse train.

If it is desired to divide the incoming pulse train by five, then line192 is connected to pin 231 and jumper 236 is connected between pin 235and pin 149. Other variations may be achieved by the selectiveconnections of line 192 to pins 230 an 231 and jumper connections fromcombinations of pins 232-235.

Division of the converter produced pulse train by a preselected division(such as two or five) introduces a tolerance factor into the circuitsince counters 132 and 133 will now count only the resulting quotient.This technique is effective to adjust the range of acceptable conditionsthat will provide a count to counter 148. For example, division by twowill result in an acceptable logic 1 for a difference of as much as twopulses between pulse trains. This technique is also effective toeliminate or minimize errors in the converterproduced pulse train. Sucherrors may emanate from noise pick up, causing the number of pulses inthe pulse train to diviate from a value that is proportional to theweight of load on platform 20.

it should also be noted that the allowable one pulse error can bereduced to zero pulse error by connecting the additional input(indicated at 250 in FIG. 3) on gate 172 to the A output terminal ofadder 142 and by removing gate 170.

In the foregoing embodiment, the pulse repetition rates of the pulsestreams that are applied to detector are constant and equal. As aresult, detector 120, in sensing changes in the number of pulses in thecompared functions of the two pulses streams, has the effect ofcomparing the lengths of successively applied pulse streams. It will beappreciated that the two eight-bit data words stored in latches 136-139are representations an functions of the number of pulses in two pulsestreams that are successively applied to the input of detector 120. Thenumber of pulses in each of the applied pulse streams, in turn, is arepresentation and function of the weight applied to platform 20.

In addition to the foregoing, detector 120 may be utilized to sensechanges in the pulse repetition frequency of serially applied pulsestreams by employing a standardized time base for generating'thelatching and reset signals together with appropriate logic. In such anapplication the pulse repetition rate may be proportional to or afunction the weight applied to a load-receiving structure in a weightingsystem in which the analog, load cell-produced, weight representingsignal is converted into a pulse train whose pulse repetition rate isproportional to or a function of the load cell-produced analog signal.

In addition, detector 120 may be utilized in comparing data samplesother than weight information. For example, it may be utilized to detectchanges in the lengths of two teletype messages. Also changes intemperature or pressure may also be sensed by detector 120 by utilizingdetector 120 with appropraite transducers.

The invention may be embodied in other specific forms without departingfrom the spirit or essential characteristics thereof. The presentembodiment is therefore to be considered in all respects as illustrativeand not restrictive, the scope of the invention being indicated by theappended claims rather than by the foregoing description, and allchanges which come within the meaning and range of equivalency of theclaims are therefore intended to be embraced therein.

What is claimed and desired to be secured by Letters Patent 1. In aweighing system, means for receiving a load to be weighed, means forproducing an electrical potential that is representative of the weightof the load applied to said load receiving means and that varies inresponse to load-induced motion of said load-receiving means, means forperiodically sampling said potential and for comparing representationsof selected samples with each other for detecting variations in themagnitude of said potential and signal utilization means controlled bysaid comparing means.

2. In a weighing apparatus having means for receiving a load to beweighed, said load-receiving means being subject to motion under theinfluence of the force exerted by the load applied thereto, and meansfor producing a series of sequentially occurring electrical pulsetrains, each of which is representative of the weight of the same loadapplied to said load-receiving means, the weight representing value ofthe pulse trains in said series being subject to variation by theforce-induced motion of said load-receiving means, the improvementcomprising electrical circuit means serially receiving said pulse trainsfor detecting variations in the weight represented by said pulse trainsfollowing application of the load to said load-receiving means.

3. The weighing apparatus defined in claim 2, wherein said electricalcircuit means includes means for providing a signal when the weightrepresenting value of the pulse trains in said series becomessubstantially stabilized.

4. The weighing apparatus defined in claim 2, wherein said pulse trainproducing means comprises means for producing an electrical analogsignal that is a function of the weight of the applied load and that issubject to variation by the forceinduced motion of said load-receivingmeans, and means for recurrently sampling said analog signal and forconverting the samples thereof into the pulse trains of said series.

5. The weighing apparatus defined in claim 4, wherein said means forconverting said samples of said analog signal pro vides each pulse trainin said series with a number of pulses that is representative of thevalue of said analog signal at that time it was sampled.

6. The weighing apparatus defined in claim 2, including means providinga read-out of the weight represented by a selected one of the pulsetrains in said series, and means controlled by said detecting means forpreventing said read-out means from providing a read-out of the weightrepresented by any one of said trains until any variations in theweightrepresenting values of said pulse trains reduce to a predeterminedmagnitude.

7. The weighing apparatus defined in claim 6, wherein said read-outmeans comprises means for printing the weight represented by theselected pulse train.

8. The weighing apparatus defined in claim 2, wherein said electricalcircuit means comprises means providing an output that is indicative ofany difference between the weights represented by selected pulse trainsin said series. 9. The weighing apparatus defined in claim 2, whereinsaid electrical circuit means comprises means for sequentiallyconverting said weight-representing pulse trains into digital signals,each of which is a function of the weight represented by the pulse trainfrom which it was derived, and means providing an output that isindicative of the difference between selected ones of said digitalsignals.

10. The weighing apparatus defined in claim 2, wherein said electricalcircuit means includes means providing an output that is indicative ofthe difference between the weight represented by each of the pulsetrains following a predetermined one of the trains in said series andthe weight represented by a selected previously occurring one of saidpulse trains.

11. In a weighing apparatus having means for receiving a load to beweighed, and means for producing a series of sequentially occurringelectrical pulse trains having a common weight-representingcharacteristic, each characteristic of the pulse trains in said seriesbeing representative of the weight-of the same load applied to saidload-receiving means, the improvement comprising electrical circuitmeans receiving said pulse trains for detecting variations in saidweight-representing characteristic.

12. The weighing apparatus defined in claim 11, wherein saidcharacteristic is the number of pulses in each pulse train.

13. In a weighing apparatus having means for receiving a load to beweighed, and means for producing a series of sequentially occurringelectrical pulse trains, each of which is representative of the weightof the same load applied to said load-receiving means, the improvementcomprising electrical circuit means serially receiving said pulse trainsfor detecting variations in the weight represented by the pulse trainsin said series.

14. The weighing apparatus defined in claim 13, wherein said pulse trainproducing means comprises means for producing a DC. signal voltage thatis a function of the weight of the load applied to said load-receivingmeans, and means for recurrently sampling said signal voltage andconverting the samples thereof into the pulse trains of said series.

15. The weighing apparatus defined in claim 14, wherein said means forconverting said samples of said analog signal provides each pulse trainin said series with a number of pulses that is representative of themagnitude of said signal voltage at that time it was sampled.

16. The weighing apparatus defined in claim 13, including meansproviding a read-out of the weight represented by a selected one of thepulse trains in said series, and means controlled by said electricalcircuit means for preventing said read-out means from providing aread-out of the weight represented by any one of said trains until anyvariations in the weight representing values of said pulse trains reduceto a predetermined magnitude.

17. The weighing apparatus defined in claim 16, wherein said read-outmeans comprises means for printing the weight represented by theselected pulse train.

18. The weighing apparatus defined in claim 13, wherein said electricalcircuit means comprises means providing an output that is indicative ofthe difference between the weights represented by selected pulse trainsin said series.

.19. The weighing apparatus'defined in claim 13, wherein said electricalcircuit means comprises means for sequentially converting saidweight-representing pulse trains into digital signals, each of which isa function of the weight represented by the pulse train from which itwas derived, and means providing an output that is indicative of thedifference between selected ones of said digital signals.

20. The weighing apparatus defined in claim 13, wherein said electricalcircuit means includes means for sequentially converting said pulsetrains in a series of digital signals, each of which is a function ofthe weight represented by the pulse train from which it was derived, andmeans providing an output that it indicative of the difference betweeneach of said digital signals following a predetermined one of thesignals in said series and a previously occurring selected one of saiddigital signals.

21. In a weighing apparatus having means -for receiving a load to beweighed, and meansfor producing a series of sequentially occurringelectrical pulse trains, each of which is representative of the weightof the same load applied to said load-receiving means, and theimprovement comprising electrical circuit means serially receiving saidpulse trains and comprising means for sequentially converting said pulsetrains into a corresponding series of sequentially occurring digitalsignals, each of which is a function of the weight represented by thepulse train from which it was derived, electrical storage means forstoring a digital signal that is derived from a selected one of saidsequentially occurring digital signals, means receiving the digitalsignal stored by said storage means and said sequentially occurringdigital signals for providing an output that varies in accordance thedifference between said selected one of said sequentially occurringdigital signals an each of the sequentially occurring digital signalsoccurring subsequent to said selected one of said signals as long as thesignal that is derived from said selected one of said digital signalsremains stored in said storage means, and signal utilization means underthe control of said output.

22. The weighing apparatus defined in claim 21, wherein said pulse trainproducing means provides each of said pulse trains with a number ofpulses that is representative of the weight of said load.

23. The weighing apparatus defined in claim 22, wherein said electricalcircuit means further includes means controlled by said output forreplacing the signal stored by said storage means with another digitalsignal that is derived from a subsequently occurring one of saidsequentially occurring digital signals whenever the difference betweenthe selected one of said digital signals and said subsequently occurringone of said digital signals exceeds a predetermined magnitude.

24. The weighing apparatus defined in claim 22, wherein saidsequentially occurring digital signals and the signal stored by saidstorage means are in binary coded form, wherein the signal stored insaid storage means is the complement of said selected one of saidsequentially occurring signals, and wherein said output providing meansis operative to add each of said sequentially occurring digital signalsto the signal stored by said storage means to provide said output with avalue that is representative of the sum of the added signals.

25. In a weighing apparatus, means for receiving a load to be weighed,means for producing an electrical potential that is a function of theload applied to said load-receiving means,

means for recurrently sampling said electrical potential to provide aseries of sequentially occurring electrical signals that arerepresentative of the sampled portions of said potential, and electricalcircuit means for detecting variations of said potential by comparingeach of said signals following a selected one of said signals with aselected previously occurring one of said signals.

UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No.3,674,097 Dated July 4. 197

Inventor(s) Richard H. Gile It is certified that error appears in theabove-identified patent and that said Letters Patent are herebycorrected as shown below:

Column 2, line 46, change "sensing" to --sensing.

Column 4, line 6, change "themoment to the moment-.

Column 8, line 37, change "pin" to pins-fl Column 8, line 45, change"EAch" to Each--.

Column 10, line 30, change "randon" to -random--. 1

Column 10, line 47, change "111111010" to -llll1910--..

" Column 10, line 49, change "0000111" to 0O0001l1-- Column 12, line lchange "he" to --the-. Column 12, line 32, change "counter" to-counters.

Column 12, line 49, change "counter" to'-counters-.

Column 14, line 21, change "counter" to -counters.

Column 14, line 29, change "on" to --one.

* Column 14, line 67, change "diviate" to --deviate--.

Column 15 line 2, change "pulses" to ----pulse-.

* Column 15, line 16, after "function" insert -of.

Column 15, line 17, change "weighting" to weighing--.

Column 10, lines 6 and 7, change' "subtraction" to --.'-substraction- 7ORM PO-1050{10-69) USCOMM-DC 60376-P69 U.S. GOVERNMENT PRINTING OFFICE:I959 0-366-334 Page 2 v e a w UNITED STATES PATENT OFFICE mmmcmn m anECIEWN;

Dated July 4;, 1972 Patent No. 3, 674, 097

Inventor(s) Richard H. Gile It is certified that error appears inthe'above-identified patent and that said Letters Patent are herebycorrected as shown below:

Column 15, lines 25 and 26, change "ppropraite" to -appropriate====.,

Column 15, line 31, after "accordence" insert -with-o Signed and sealedthis 17th day of April 1973.

(SEAL) Attest:

EDWARD M.PLETCHER,JR. I ROBERT GOTTSCHALK Attesting Officer Commissionerof Patents FORM PO-IOSO (10-69) USCOMWDC 60376 P69 9 ".5. GOVERNMENTPRINTING OFFICE: I959 0-366-331

1. In a weighing system, means for receiving a load to be weighed, meansfor producing an electrical potential that is representative of theweight of the load applied to said load receiving means and that variesin response to load-induced motion of said load-receiving means, meansfor periodically sampling said potential and for comparingrepresentations of selected samples with each other for detectingvariations in the magnitude of said potential and signal utilizationmeans controlled by said comparing means.
 2. In a weighing apparatushaving means for receiving a load to be weighed, said load-receivingmeans being subject to motion under the influence of the force exertedby the load applied thereto, and means for producing a series ofsequentially occurring electrical pulse trains, each of which isrepresentative of the weight of the same load applied to saidload-receiving means, the weight representing value of the pulse trainsin said series being subject to variation by the force-induced motion ofsaid load-receiving means, the improvement comprising electrical circuitmeans serially receiving said pulse trains for detecting variations inthe weight represented by said pulse trains following application of theload to said load-receiving means.
 3. The weighing apparatus defined inclaim 2, wherein said electrical circuit means includes means forproviding a signal when the weight representing value of the pulsetrains in said series becomes substantially stabilized.
 4. The weighingapparatus defined in claim 2, wherein said pulse train producing meanscomprises means for producing an electrical analog signal That is afunction of the weight of the applied load and that is subject tovariation by the force-induced motion of said load-receiving means, andmeans for recurrently sampling said analog signal and for converting thesamples thereof into the pulse trains of said series.
 5. The weighingapparatus defined in claim 4, wherein said means for converting saidsamples of said analog signal provides each pulse train in said serieswith a number of pulses that is representative of the value of saidanalog signal at that time it was sampled.
 6. The weighing apparatusdefined in claim 2, including means providing a read-out of the weightrepresented by a selected one of the pulse trains in said series, andmeans controlled by said detecting means for preventing said read-outmeans from providing a read-out of the weight represented by any one ofsaid trains until any variations in the weight-representing values ofsaid pulse trains reduce to a predetermined magnitude.
 7. The weighingapparatus defined in claim 6, wherein said read-out means comprisesmeans for printing the weight represented by the selected pulse train.8. The weighing apparatus defined in claim 2, wherein said electricalcircuit means comprises means providing an output that is indicative ofany difference between the weights represented by selected pulse trainsin said series.
 9. The weighing apparatus defined in claim 2, whereinsaid electrical circuit means comprises means for sequentiallyconverting said weight-representing pulse trains into digital signals,each of which is a function of the weight represented by the pulse trainfrom which it was derived, and means providing an output that isindicative of the difference between selected ones of said digitalsignals.
 10. The weighing apparatus defined in claim 2, wherein saidelectrical circuit means includes means providing an output that isindicative of the difference between the weight represented by each ofthe pulse trains following a predetermined one of the trains in saidseries and the weight represented by a selected previously occurring oneof said pulse trains.
 11. In a weighing apparatus having means forreceiving a load to be weighed, and means for producing a series ofsequentially occurring electrical pulse trains having a commonweight-representing characteristic, each characteristic of the pulsetrains in said series being representative of the weight of the sameload applied to said load-receiving means, the improvement comprisingelectrical circuit means receiving said pulse trains for detectingvariations in said weight-representing characteristic.
 12. The weighingapparatus defined in claim 11, wherein said characteristic is the numberof pulses in each pulse train.
 13. In a weighing apparatus having meansfor receiving a load to be weighed, and means for producing a series ofsequentially occurring electrical pulse trains, each of which isrepresentative of the weight of the same load applied to saidload-receiving means, the improvement comprising electrical circuitmeans serially receiving said pulse trains for detecting variations inthe weight represented by the pulse trains in said series.
 14. Theweighing apparatus defined in claim 13, wherein said pulse trainproducing means comprises means for producing a D.C. signal voltage thatis a function of the weight of the load applied to said load-receivingmeans, and means for recurrently sampling said signal voltage andconverting the samples thereof into the pulse trains of said series. 15.The weighing apparatus defined in claim 14, wherein said means forconverting said samples of said analog signal provides each pulse trainin said series with a number of pulses that is representative of themagnitude of said signal voltage at that time it was sampled.
 16. Theweighing apparatus defined in claim 13, including means providing aread-out of the weight represented by a selected one of the pulse trainsin said series, and means controlled by said Electrical circuit meansfor preventing said read-out means from providing a read-out of theweight represented by any one of said trains until any variations in theweight representing values of said pulse trains reduce to apredetermined magnitude.
 17. The weighing apparatus defined in claim 16,wherein said read-out means comprises means for printing the weightrepresented by the selected pulse train.
 18. The weighing apparatusdefined in claim 13, wherein said electrical circuit means comprisesmeans providing an output that is indicative of the difference betweenthe weights represented by selected pulse trains in said series.
 19. Theweighing apparatus defined in claim 13, wherein said electrical circuitmeans comprises means for sequentially converting saidweight-representing pulse trains into digital signals, each of which isa function of the weight represented by the pulse train from which itwas derived, and means providing an output that is indicative of thedifference between selected ones of said digital signals.
 20. Theweighing apparatus defined in claim 13, wherein said electrical circuitmeans includes means for sequentially converting said pulse trains in aseries of digital signals, each of which is a function of the weightrepresented by the pulse train from which it was derived, and meansproviding an output that it indicative of the difference between each ofsaid digital signals following a predetermined one of the signals insaid series and a previously occurring selected one of said digitalsignals.
 21. In a weighing apparatus having means for receiving a loadto be weighed, and means for producing a series of sequentiallyoccurring electrical pulse trains, each of which is representative ofthe weight of the same load applied to said load-receiving means, andthe improvement comprising electrical circuit means serially receivingsaid pulse trains and comprising means for sequentially converting saidpulse trains into a corresponding series of sequentially occurringdigital signals, each of which is a function of the weight representedby the pulse train from which it was derived, electrical storage meansfor storing a digital signal that is derived from a selected one of saidsequentially occurring digital signals, means receiving the digitalsignal stored by said storage means and said sequentially occurringdigital signals for providing an output that varies in accordance thedifference between said selected one of said sequentially occurringdigital signals an each of the sequentially occurring digital signalsoccurring subsequent to said selected one of said signals as long as thesignal that is derived from said selected one of said digital signalsremains stored in said storage means, and signal utilization means underthe control of said output.
 22. The weighing apparatus defined in claim21, wherein said pulse train producing means provides each of said pulsetrains with a number of pulses that is representative of the weight ofsaid load.
 23. The weighing apparatus defined in claim 22, wherein saidelectrical circuit means further includes means controlled by saidoutput for replacing the signal stored by said storage means withanother digital signal that is derived from a subsequently occurring oneof said sequentially occurring digital signals whenever the differencebetween the selected one of said digital signals and said subsequentlyoccurring one of said digital signals exceeds a predetermined magnitude.24. The weighing apparatus defined in claim 22, wherein saidsequentially occurring digital signals and the signal stored by saidstorage means are in binary coded form, wherein the signal stored insaid storage means is the complement of said selected one of saidsequentially occurring signals, and wherein said output providing meansis operative to add each of said sequentially occurring digital signalsto the signal stored by said storage means to provide said output with avalue that is representative of the suM of the added signals.
 25. In aweighing apparatus, means for receiving a load to be weighed, means forproducing an electrical potential that is a function of the load appliedto said load-receiving means, means for recurrently sampling saidelectrical potential to provide a series of sequentially occurringelectrical signals that are representative of the sampled portions ofsaid potential, and electrical circuit means for detecting variations ofsaid potential by comparing each of said signals following a selectedone of said signals with a selected previously occurring one of saidsignals.